The density of microelectronic devices on a semiconductor substrate may be increased by decreasing the size or line width of the microelectronic devices. The decrease in line width allows a large number of microelectronic devices to be formed on the semiconductor substrate. As a result, the computing's power and speed of the semiconductor combined maybe greatly improved.
In order to decrease the line width of a microelectronic device, the lateral dimensions of conductor, semiconductor and insulator regions forming each a microelectronic device must be reduced. For example, the lateral width of structures such as vias and interconnects must be reduced in order to achieve microelectronic devices of reduced geometries. Conductive vias and interconnects are utilized within microelectronic devices to form contact openings that allow an overlying conductive layer to electrically contact an underlying conductive layer through an intermediate layer such as a dielectric layer. Such contact openings may be filled with plugs of conductive material designed to electrically connect the two conductive layers.
One commonly used conductive material in plug applications designed to fill contact openings is tungsten. The formation of tungsten plug structures requires first depositing a layer of barrier material such as titanium nitride (TiN) to avoid damaging a titanium adhesion layer typically present where the contact opening meets the substrate. An undamaged adhesion layer is essential to provide a low contact resistance between a plug and the underlying substrate. Traditionally, increasing the thickness of the barrier layer was seen as a viable means of insuring that the adhesion layer remained free of defects during plug formation. However, as the lateral dimensions of contact openings continue to decrease, the via resistance of such openings reaches a prohibitive level if a significant portion of their widths are taken up with the thickness of the barrier layer. A problem therefore arises as to how to maintain the protective characteristics of the barrier layer at the significantly reduced thicknesses demanded by ever shrinking device geometries.